SCKDL=000
SPI Clock Delay Register
| SCKDL | RSPCK Delay Setting 0 (000): 1 RSPCK 1 (001): 2 RSPCK 2 (010): 3 RSPCK 3 (011): 4 RSPCK 4 (100): 5 RSPCK 5 (101): 6 RSPCK 6 (110): 7 RSPCK 7 (111): 8 RSPCK |
| Reserved | These bits are read as 00000. The write value should be 00000. |